There are times when two systems or components operating at two different clocks rates need to be interfaced. Such an interface is difficult in the sense that the design becomes asynchronous at the boundary of interface. Clock drift for either system or component needs to be accounted for to avoid overflow or underflow of buffers at the interface. Various clock drift compensation techniques exist, which involve estimating the clock drift and thereafter compensating accordingly for the estimated clock drift. Unfortunately, continuously estimating clock drift is computationally expensive.